The present Invention relates generally to signal processing and, more particularly, to novel digital correlation systems.
A digital correlator is a device capable of detecting the presence of a replica of a finite length reference binary code sequence in a relatively long signal sequence of bits. These devices have many applications such as in signal processing, spread spectrum communications, code synchronization/detection, and error correction coding.
An N-bit digital correlator operates to compare an incoming data stream to N bits of a reference word. Although the following discussion will be concerned with the comparison of serial bit streams it is to be understood that multiple bit digital data can be processed in parallel. The correlator presents a measure of the amount of correlation between corresponding bits in the signal data stream and the reference word. One such measure is the number of bit agreements but others can also be used. Whenever N signal bits correspond exactly to the N-bit reference word, perfect correlation occurs and the correlator output will be a maximum. Often times it is useful for the correlator to signal not only the presence or lack of perfect correlation but also to quantify partial correlation. One such measure would be the number of agreements between the corresponding bits in the data stream and the reference word. Other measures can also be used.
A simplified logic diagram of a typical prior art digital correlator 10 is shown in FIG. 1. In the digital correlator 10, a signal register 20 is a shift register containing N elements 22, 24, 26, and 28 for storage of binary bits. Binary data is fed into one end of the shift register chain of the signal register 20 on a serial input signal line 30. At each clock pulse appearing on the signal clock line 32, the binary bit on the serial input signal line 30 is written into the highest order storage element 22. Simultaneously data already existing in the storage elements 22, 24 and 26 are shifted to the next lower storage elements 24, 26 and 28, respectively. Data already in the lowest order element 28 is lost upon a shift. Thus after N cycles of the signal clock, the signal register 20 contains N bits of the data stream (s.sub.N,s.sub.N-1, . . . s.sub.2,s.sub.1). The signal clock is presumed to be synchronized with the data in the signal bit stream flowing on the serial input signal line 30. It is also presumed that the data stream is considerably longer than the N-bit capacity of the signal register 20, so that the signal register 20 contains the N latest bits in the data stream. At each signal clock cycle, the data in the signal register 20 is shifted by one storage element to reflect the recently arrived bit. Each storage element 22, 24, 26, and 28 has a respective output line 34, 36, 38 and 40 that carries a signal indicative of the most recent data bit in the respective storage element.
The digital correlator 10 of FIG. 1 further includes a reference register 50 which is a shift register similar to the signal register 20 and which also includes N storage elements 52, 54, 56, and 58. A reference clock signal appearing on a reference clock line 60 controls the reference word input to the reference register 50 during an initialization phase when an N-bit reference word (r.sub.n, r.sub.n-1, . . . r.sub.2, r.sub.1) is serially impressed on the reference word input line 62 controlling the input to the reference register 50. Output lines 64, 66, 68 and 70 carry the current data in the storage elements 52, 54, 56 and 58, respectively. It should be appreciated that the reference word is prestored in the reference register 50 and used for comparison with the signal bit stream. However, the contents of the reference register 50 can be modified by means of the reference input 62 and reference clock input 60.
The output lines 34-40 and 64-70 of the respective signal 20 and reference 50 registers are pairwise connected to equivalence gates 72, 74, 76 and 78, respectively, each of which are exclusive-OR gates with a negated output. An equivalence gate produces a positive output only when its two inputs are the same, whether they both are 0 or 1. The pairwise connection is between storage elements of the same order in the two registers 20 and 50.
The outputs of the equivalence gates 72, 74, 76 and 78 are connected to the inputs of a summation or adder circuit 80. The adder circuit 80 adds all the outputs of the equivalence gates 72-78 and produces the sum on its output line 82. This sum represents the number of agreements "A" between the serial data bit stream and the reference word. The maximum value of "A" is thus "N". Any lesser finite value represents partial correlation between the data stream and the reference word. In applications such as spread spectrum communications, a more desirable measure of correlation is the difference, A-D, between bit agreements "A" and disagreements "D". For a sequence of N bits, this conversion is simply made by the algebraic relation A-D=2A-N. The output of a correlator can be either digital, in which case a multiple-line bus can carry a digital value, or it can be analog, in which case the voltage on the output line represents the number of bit agreements.
Digital correlators currently available from manufacturers have desirable properties with respect to reliability, maintainability, cost and the application of high scale integrated circuit techniques. They are capable of correlating very long reference sequences without degradation in signal levels. However one of the factors limiting their application has been their low speed or bandwidth capability relative to other technologies such as surface acoustic wave devices. For example, one of the fastest digital correlators presently available is the TDC 1023J produced by TRW LSI Products. This correlator operates on 64-bit data sequences and produces a seven-bit digital output while operating at a clock rate of up to 20 MHz. Many applications require correlation speeds greater than that presently available in digital correlators.